In layout design of a semiconductor integrated circuit (LSI: large scale integration), for example, an arrangement process is performed so that component circuits called standard cells, macro cells, and the like having transistors therein are arranged. In the layout design, a wiring process is performed so that the arranged component circuits are connected to each other by using a wiring pattern. Thus, layout data indicating a physical form pattern of an LSI is obtained.
In the layout design, it is determined whether or not the layout data complies with physical design rules called design rules. The determination as to whether or not the physical design rules are complied with is made by using a verification application called a design rule check (DRC) tool. When an error is detected by using a DRC tool, the layout data is modified.
One of the physical design rules is a density rule. The density rule stipulates the density of the circuit pattern disposed in a layout available area. The density is defined, for example, by using an area ratio in which figures corresponding to a circuit pattern occupy a given partitioned area. A density error affects, for example, a chemical mechanical planarization (CMP) process in manufacture of an LSI. Therefore, the density of the layout pattern is desirably uniform in each layer. When a difference in density is large, it is difficult to polish an LSI uniformly in the CMP process, and manufacturing defects and a decrease in yield may occur. For example, in a given wiring layer, excessive polishing may be performed in the CMP process on an area having a too low layout density, and a short circuit with a lower wiring layer may occur. In addition, for example, in a given wiring layer, polishing is not performed in the CMP process on an area having a too high layout density. Therefore, a short circuit between wiring lines in the same wiring layer may occur.
It may be difficult to comply with the density rule only by using the physical form pattern of an LSI. Therefore, the following technique of the related art is used. For example, the density rule is complied with by disposing a dummy pattern in an available area in which a physical form pattern is not disposed. A dummy pattern is disposed, for example, by using an application such as a dummy generating tool which is capable of disposing a dummy pattern automatically after completion of the arrangement process and the wiring process.
In the related art, the following technique is used. Arrangement candidate areas, in each of which, on a lower level, no dummy patterns are disposed between a circuit block boundary and a dummy pattern, are present. A dummy pattern is disposed on an upper level in a portion obtained by combining some of the arrangement candidate areas. The circuit blocks having the combined arrangement candidate areas are in contact with each other. In the related art, a technique is used in which, in a semiconductor apparatus having a multilayer wiring configuration, a dummy pattern oriented in a direction difference from that of a dummy pattern formed in a wide wiring gap is formed in a narrow wiring gap.
However, a problem arises in that efficiency in the layout design may be deteriorated in a dummy pattern generating process. For example, when dummy patterns are generated at a time for the entire design target circuit, it takes time to generate dummy patterns so as to satisfy all of the physical design rules including various rules. In addition, for example, when a layout operation is performed by using a bottom-up hierarchical design method in which a semiconductor integrated circuit divided into multiple hierarchical levels is designed from a lower level to an upper level, a density error may occur on an upper level regardless of no density errors on the lower levels. In this case, to clear a density error on an upper level, redesign may take place. For example, the design process is returned to a lower level, and the physical form pattern and the dummy pattern may be modified.
The followings are reference documents.
[Document 1] Japanese Laid-open Patent Publication No. 2016-105446 and
[Document 2] Japanese Laid-open Patent Publication No. 2012-212697.